CENG 342/342L, Section M001, Hemmelman, 2010SP - Course Materials

University Directory
Computer Engineering (CENG)
Hemmelman, Brian T - Associate Professor

Syllabus
My Teaching Philosophy
The Spartan3 Board
Xilinx WEBPACK Software Tools
Explicit Link to ModelSim Xilinx Edition
Xilinx and ModelSim Installation Instructions (Earlier Version)
Xilinx and ModelSim Introductory Tutorial
Lab Report Grading Sheet
Lab Grading Details
Link to Downloadable Microsoft Journal Viewer
Introduction to Programmable Logic
Introduction to VHDL
2 x 1 Multiplexer Version 1
2 x 1 Multiplexer Version 2
2 x 1 Multiplexer Version 3
4 x 1 Multiplexer Version 1
4 x 1 Multiplexer Version 2
4 x 1 Multiplexer Version 3
4 x 1 Multiplexer Version 4
4 x 1 Multiplexer Version 5
16 x 1 Multiplexer Version 1
16 x 1 Multiplexer Version 2
N x 1 Multiplexer Using "generic"
74151 Multiplexer
1 x 2 Decoder Version 1
1 x 2 Decoder Version 2
3 x 8 Decoder Version 1
3 x 8 Decoder Version 2
3 x 8 Decoder Version 3
1-Bit Magnitude Comparator Version 1
1-Bit Magnitude Comparator Version 2
4-Bit Magnitude Comparator Version 1
4-Bit Magnitude Comparator Version 2
4-Bit Magnitude Comparator Version 3
4-Bit Magnitude Comparator Version 4
BCD-to-Decimal Decoder Version 1
BCD-to-Decimal Decoder Version 2
BCD-to-Decimal Decoder Version 3
BCD-to-Seven Segment Display Decoder
8-Bit Serial-In/Serial-Out Register Version 1
8-Bit Serial-In/Serial-Out Register Version 2
8-Bit Serial-In/Serial-Out Register Version 3
8-Bit Serial-In/Serial-Out Register Version 4
8-Bit Serial-In/Parallel-Out Register
8-Bit Parallel Load Shift Register
Octal Tristate Latch Version 1
Octal Tristate Latch Version 2
Octal Tristate Latch Version 3
4-Bit Adder Using Component Instantiation
4-Bit Adder Using Components and Generates
Using TCL Macros to Perform ModelSim Simulations
4-Bit Counter with Parallel Load
4-Bit Down Counter with Generic
4-Bit Counter Using Std_Logic
Arbitrary Count Counter
Xilinx Timing Simulation Tutorial
5 MHz Counter Version 1
5 MHz Counter Version 2
5 MHz Counter Version 3
7-Segment Display Example Using Component Instantiation
7-Segment Display Example Using Component Instantiation and Packages
Homework Set #1
Laboratory #1
Sample Lab Report
Sample Lab Report #2
Homework Set #2
Laboratory #2
Homework #3
Register File
FIFO
Exam #1 Study Guide
Lab #3
Finite State Machine Review Notes (Journal Format)
Finite State Machine Review Notes (pdf Format)
State Machine Example 1 Version 1
State Machine Example 1 Version 2
State Machine Example 2
State Machine Example 3
Vending Machine Moore Version
Vending Machine Mealy Version
State Machine Template
Lab #4
Lab #4 Notes (pdf Format)
Homework Set #4
Lecture Notes 03/19/10 (Journal Format)
Lecture Notes 03/19/10 (pdf Format)
Lecture Notes 03/22/10 (Journal Format)
Lecture Notes 03/22/10 (pdf Format)
4 x 4 Unsigned Multiplier
Lecture Notes 03/24/10 (Journal Format)
Lecture Notes 03/24/10 (pdf Format)
Homework Set #5
Lecture Notes 03/26/10 (Journal Format)
Lecture Notes 03/26/10 (pdf Format)
Lab #5
Lecture Notes 04/07/10 (Journal Format)
Lecture Notes 04/07/10 (pdf Format)
Lecture Notes 04/14/10 (Journal Format)
Lecture Notes 04/14/10 (pdf Format)
Exam #2 Study Guide
Lecture Notes 04/16/10 (Journal Format)
Lecture Notes 04/16/10 (pdf Format)
Lab #6
Exam #2 Bonus Question
555 Timer Notes
Final Exam Study Guide

Contact: South Dakota School of Mines and Technology
http://www.hpcnet.org/sdsmt/directory/courses/2010sp/ceng342/342LM001