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CSC 317/317L, Section M001, Hemmelman, 2012SP - Course Materials University Directory Computer Science (CSC) Hemmelman, Brian T - Associate Professor Syllabus My Teaching Philosophy The Spartan 3 FPGA Board Xilinx WEBPACK Software Tools Xilinx Processor a la Carte CSC 317 Slide Set #1 Lab Report Grading Sheet Lab Report Grading Details Example Lab Report #1 Example Lab Report #2 Example Lab Report #3 Example Lab Report #4 Xilinx ISE and Spartan 3 FPGA Board Tutorial Introduction to Programmable Logic Introduction to VHDL 2 x 1 Multiplexer Version 1 2 x 1 Multiplexer Version 2 2 x 1 Multiplexer Version 3 4 x 1 Multiplexer Version 1 4 x 1 Multiplexer Version 2 4 x 1 Multiplexer Version 3 4 x 1 Multiplexer Version 4 4 x 1 Multiplexer Version 5 16 x 1 Multiplexer Version 1 16 x 1 Multiplexer Version 2 N x 1 Multiplexer Using "generic" 74151 Multiplexer 1 x 2 Decoder Version 1 1 x 2 Decoder Version 2 3 x 8 Decoder Version 1 3 x 8 Decoder Version 2 3 x 8 Decoder Version 3 1-Bit Magnitude Comparator Version 1 1-Bit Magnitude Comparator Version 2 4-Bit Magnitude Comparator Version 1 4-Bit Magnitude Comparator Version 2 4-Bit Magnitude Comparator Version 3 4-Bit Magnitude Comparator Version 4 BCD-to-Decimal Decoder Version 1 BCD-to-Decimal Decoder Version 2 BCD-to-Decimal Decoder Version 3 BCD-to-Seven Segment Display Decoder 8-Bit Serial-In/Serial-Out Register Version 1 8-Bit Serial-In/Serial-Out Register Version 2 8-Bit Serial-In/Serial-Out Register Version 3 8-Bit Serial-In/Serial-Out Register Version 4 8-Bit Serial-In/Parallel_Out Register 8-Bit Parallel Load Shift Register Octal Tristate Latch Version 1 Octal Tristate Latch Version 2 Octal Tristate Latch Version 3 4-Bit Adder Using Component Instantiation 4-Bit Adder Using Components and Generates Lab #1 Lab #2 7-Segment Display Example Using Component Instantiation 7-Segment Display Example Using Component Instantiation and Packages 4-Bit Counter with Parallel Load 4-Bit Down Counter with Generic 4-Bit Counter Using std_logic Arbitrary Count Counter 5 MHz Counter Version 1 5 MHz Counter Version 2 5 MHz Counter Version 3 Homework Set #1 Register File FIFO (First-In First-Out) Buffer Niagara Processor Info Niagara II Processor Info Niagara III Processor Info Finite State Machines Review State Machine Example 1 Version 1 State Machine Example 1 Version 2 State Machine Example 2 State Machine Example 3 Vending Machine Moore Version Vending Machine Mealy Version State Machine Template Switch Debouncing State Machine Homework Set #2 Lab #3 CSC 317 Memory Hierarchy Notes Finite State Machines with Datapath Homework Set #2 Solutions Exam #1 Study Guide Lab #4 SRAM Notes Homework Set #3 Homework Set #3 Solutions MIPS Processor Introductory Slides Lab #5 Homework Set #4 Homework Set #4 Solutions MIPS Processor Hardware Notes (so far...) Storage and I/O Notes Pipelining Notes Lab #6 Exam #2 Study Guide Exam #2 Solutions Final Exam Study Guide Contact: South Dakota School of Mines and Technology http://www.hpcnet.org/sdsmt/directory/courses/2012sp/csc317/317LM001
http://www.hpcnet.org/sdsmt/directory/courses/2012sp/csc317/317LM001